View ICS93738_103880.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS93738
DDR and SDRAM Buffer
Recommended Application: DDR & SDRAM fanout buffer, for VIA P4X/KT266/333 chipsets. Product Description/Features: * * * * * * * * Low skew, fanout buffer 1 to 12 differential clock distribution I2C for functional and output control Feedback pin for input to output synchronization Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + 2 DDR DIMMs Frequency supports up to 200MHz (DDR400) Supports Power Down Mode for power mananagement CMOS level control signal input
Pin Configuration
FB_OUT VDD3.3_2.5 GND DDRT0_SDRAM0 DDRC0_SDRAM1 DDRT1_SDRAM2 DDRC1_SDRAM3 VDD3.3_2.5 GND DDRT2_SDRAM4 DDRC2_SDRAM5 VDD3.3_2.5 BUF_IN GND DDRT3_SDRAM6 DDRC3_SDRAM7 VDD3.3_2.5 GND DDRT4_SDRAM8 DDRC4_SDRAM9 DDRT5_SDRAM10 DDRC5_SDRAM11 VDD3.3_2.5 SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEL_DDR* VDD2.5 GND DDRT11 DDRC11 DDRT10 DDRC10 VDD2.5 GND DDRT9 DDRC9 VDD2.5 PD#* GND DDRT8 DDRC8 VDD2.5 GND DDRT7 DDRC7 DDRT6 DDRC6 GND SCLK
Switching Characteristics: * OUTPUT - OUTPUT skew: <100ps SDRAM OUTPUT - OUTPUT skew: <150ps DDR * Output Rise and Fall Time for DDR outputs: 600ps 950ps * DUTY CYCLE: 47% - 53% DDR DUTY CYCLE: 45%- 55% SDRAM
48-Pin SSOP
*Internal Pull-up Resistor of 120K to VDD
Block Diagram
FB_OUT DDRT0_SDRAM0 DDRC0_SDRAM1 DDRT1_SDRAM2 DDRC1_SDRAM3
Functionality
MODE DDR Mode DDR/SD Mode PIN 48 VDD 3.3_2.5 2.5V PIN 4, 5, 6, 7, 10, 11, 15, 16, 19, 20, 21, 22 These outputs will be DDR outputs These outputs will be standard SDRAM outputs
BUF_IN
SEL_DDR=1
SCLK SDATA SEL_DDR* PD#
Control Logic
DDRT2_SDRAM4 DDRC2_SDRAM5 DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9 DDRT5_SDRAM10 DDRC5_SDRAM11 DDRT(11:6) DDRC (11:6)
SEL_DDR=0
3.3V
0689A--01/09/03
ICS93738
ICS93738
Pin Descriptions
PIN NUMBER 1 2, 8, 12, 17, 23, 3, 9, 14, 18, 26, 31, 35, 40, 46 45, 43, 39, 34, 30, 28, 44, 42, 38, 33, 29, 27, 21, 19, 15, 10, 6, 4 PIN NAME FB_OUT VDD3.3_2.5 GND DDRT (11:6) DDRC (11:6) DDRT (5:0) SDRAM (10, 8, 6, 4, 2, 0) TYPE OUT PWR PWR OUT OUT OUT OUT IN I/O IN PWR DESCRIPTION Feedback output, dedicated for external feedback 2.5V or 3.3V voltage supply to pins 4, 5, 6, 7, 10, 11, 15 , 16, 19 , 20, 21, 22 Ground "Tr ue" Clock of differential pair outputs. "Complementory" clocks of differential pair outputs. "Tr ue" Clock of differential pair outputs, or 3.3V SDRAM clock outputs depending on SEL_DDR input "Complementory" clocks of differential pair outputs, or 3.3V SDRAM clock outputs depending on SEL_DDR input Single ended buffer input Data pin for I2C circuitry 5V tolerant Clock input of I2C input, 5V tolerant input 2.5V voltage supply Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled. The latency of the power down will not be greater t h a n 3 m s. Select input for DDR mode or DDR/SD mode 0=DDR/SD mode 1=DDR mode
DDRC (5:0) 22, 20, 16, 11, 7, 5 SDRAM (11, 9, 7, 5, 3, 1,) 13 24 25 32, 37, 41, 47 BUF_IN SDATA SCLK VDD2.5
36
PD#
IN
48
SEL_DDR
IN
0689A--01/09/03
2
ICS93738
Byte 6: Output Control (1= enable, 0 = disable)
Byte 7: Output Control (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 48 45, 44 43, 42 39, 38 34, 33
PWD 1 1 1 1 1 1 1 1
DESCRIPTION SEL_DDR (Read back only) (Reserved) (Reserved) (Reserved) DDRT11, DDRC11 DDRT10, DDRC10 DDRT9, DDRC9 DDRT8, DDRC8
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 30, 29 28, 27 21, 22 19, 20 15, 16 10, 11 6, 7 4, 5
PWD DESCRIPTION 1 DDRT7, DDRC7 1 DDRT6, DDRC6 DDRT5, SDRAM10 1 DDRC5_SDRAM11 DDRT4_SDRAM8 1 DDRC4_SDRAM9 DDRT3_SDRAM6 1 DDRC3_SDRAM7 DDRT2_SDRAM4 1 DDRC2_SDRAM5 DDRT1_SDRAM2 1 DDRC1_SDRAM3 DDRT0_SDRAM1 1 DDRC0_SDRAM0
0689A--01/09/03
3
ICS93738
Absolute Maximum Ratings
Supply Voltage (VDD & VDD2.5) . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND -0.5 V to VDD +0.5 V 0C to +85C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output Parameters - SDRAM
SEL_DDR=0, SDRAM Outputs, VDD3.3_2.5 = 3.3V, TA = 0 - 85 C (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current Output Low Current High-level Output Voltage Low-level Output Voltage Input Capacitance
1 o
SYMBOL IIH IIL IDD3.3_2.5 IDD2.5 IDDPD IOH IOL VOH VOL CIN
CONDITIONS VIN = VDD or GND VIN = VDD or GND CL = 0 pF at 133 MHz CL = 0 pF at 133 MHz CL = 0 pF VDD = 3.3V, VOUT = 1V VDD = 3.3V, VOUT = 1.2V VDD = 3.3V, IOH = -12mA VDD = 3.3V, IOL = 12mA VIN = VDD or GND
MIN -100
TYP
MAX 10
UNITS A A mA mA A mA mA V
170 90 0 26 2
250 200 10 -18
0.4
V pF
1. Guaranteed by design, not 100% tested in production.
Recommended Operating Conditions - SDRAM
SEL_DDR=0, SDRAM Outputs, VDD3.3_2.5 = 3.3V, TA = 0 - 85oC (unless otherwise stated) PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Input Voltage Level SYMBOL VDD3.3_2.5 VDD2.5 VIH VIL VIN SEL_DDR, PD# inputs SEL_DDR, PD# inputs CONDITIONS MIN 3 2.5 2 0.8 TYP 3.3 2.5 MAX 3.6 2.7 UNITS V V V V
0689A--01/09/03
4
ICS93738
Electrical Characteristics - Input / Supply / Common Output Parameters - DDR
SEL_DDR=1, DDR/DDR_SDRAM Outputs, VDD3.3_2.5 = 2.5V, TA = 0 - 85oC (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current Output High Current High-level Output Voltage Low-level Output Voltage Output differential-pair 1 crossing voltage Input Capacitance1 SYMBOL IIH IIL IDD3.3_2.5 IDD2.5 IDDPD IOH IOL VOH VOL CIN CIN VIN = VDD or GND CONDITIONS VIN = VDD or GND VIN = VDD or GND CL = 0 pF at 133 MHz CL = 0 pF at 133 MHz CL = 0 pF VDD = 2.5V, VOUT = 1V VDD = 2.5V, VOUT = 1.2V VDD = 2.5V, IOH = -12mA VDD = 2.5V, IOL = 12mA VDD/2 0.1 1.2 26 1.7 0.46 VDD/2 + 0.1 -100 125 90 0 200 200 10 -18 MIN TYP MAX 10 UNITS A A mA mA A mA mA V V V pF
1. Guaranteed by design, not 100% tested in production.
Recommended Operating Conditions - DDR
SEL_DDR=1, DDR/DDR_SDRAM Outputs, VDD3.3_2.5 = 2.5V, TA = 0 - 85oC (unless otherwise stated) PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Input Voltage Level SYMBOL VDD3.3_2.5 VDD2.5 VIH VIL VIN SEL_DDR, PD# inputs SEL_DDR, PD# inputs CONDITIONS MIN 2.3 2.5 2 0.8 TYP 2.5 2.5 MAX 2.7 2.7 UNITS V V V V
0689A--01/09/03
5
ICS93738
Switching Characteristics
TA = 0 - 85 C PARAMETER Operating Frequency Input clock duty cycle Output to output Skew (DDR outputs) Output to output Skew1 (SDRAM outputs) Duty Cycle1,3 (DDR outputs) Duty Cycle1,3 (SDRAM outputs) Rise Time, Fall Time1 (DDR outputs) Rise Time, Fall Time (SDRAM outputs)
1 1 o
SYMBOL dtin TskewDDR TskewSD DCDDR DCSD trd, tfd trs, tfs tPLH tPHL
CONDITIONS
MIN 66 40
TYP 133 50 80 70
MAX 200 60 150 100 52 53 55 950 1.7 2.5 2.5
UNITS MHz % ps ps % % ps ns ns ns
VT = 50%, Not including FB_OUT to outputs VT = 1.5V VT = 50%, 66 MHz to 100 MHz , w/loads VT = 50%, 101 MHz to 167 MHz, w/loads VT = 1.5V, w/loads Single-ended 20 - 80 % 133 MHz, Load = 120 / 12 pF Single-ended VOL = 0.4V, VOH = 2.4V 133 MHz, Load = 12 pF Input edge greater than 1V/ns Input edge greater than 1V/ns 48 47 45 600 0.5
49 50 50 800 1.5 2 1.9
SDRAM Buffer LH Propagation Delay1,2 SDRAM Buffer HL Propagation Delay1,2
1. Guaranteed by design, not 100% tested in production. 2. Refers to transistion on non-inverting output. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t2 / t1, where the cycle time (t1) decreases as the frequency increases.
Switching Waveforms
Duty Cycle Timing
t1 t2
1.5V 1.5V 1.5V
SDRAM Buffer LH and HL Propagation Delay
1.5V INPUT 1.5V
1.5V OUTPUT
1.5V
t6
0689A--01/09/03
t7
6
ICS93738
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D4(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
ACK
Byte 1
Byte 1
ACK
ACK
Byte 2
Byte 2
ACK
ACK
Byte 3
Byte 3
ACK
ACK
Byte 4
Byte 4
ACK
ACK
Byte 5
Byte 5
ACK
ACK
Byte 6
Byte 6
ACK
ACK
Byte 7
Byte 7
Stop Bit
ACK
Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
0689A--01/09/03
7
ICS93738
N
c
300 mil SSOP SYMBOL A A1 b c D E E1 e h L N VARIATIONS N 48 D mm. MIN 15.75 MAX 16.00 MIN .620 D (inch) MAX .630 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
L
INDEX AREA
E1
E
12 D h x 45
A A1
-Ce
b SEATING PLANE .10 (.004) C
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP
10-0034
Ordering Information
ICS93738yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0689A--01/09/03
8

▲Up To Search▲

Price & Availability of ICS93738

	To Download ICS93738 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .